1. Field of the Invention
The present invention relates to a semiconductor memory which is required to be operated at a high speed, and more particularly to an output buffer structure of the memory.
2. Description of the Related Art
A hyper page mode (hereinafter referred to as HPM) is one the of high speed operation modes of a DRAM. In this mode, when data stored in an internal memory cell or a register is consecutively accessed in accordance with an address signal defined by means of a predetermined clock signal (/CAS: a fall signal of CAS) as a trigger, the accessed data is output, as it is, in a clock cycle between the triggers of a clock signal and the next clock signal. The mode is also called an extended data output mode (EDO).
FIG. 1 is a waveform diagram in which data output states in the HPM and the conventional page mode in a DRAM are compared. In this specification, the page mode is called a fast page mode and abbreviated as (FPM). An address signal ADD is divided into a row address (ROW.ADR) and a column address (COL.ADR). The row address is defined by a row selecting signal /RAS (a fall signal of RAS) and the column address is defined by a column selecting signal /CAS (a fall signal of CAS). The column address is consecutively changed, and data in a memory cell (not shown) accessed with the addresses is indicated as an output I/O.
In FIG. 1, the waveform determined by an access time (TCAC) from the signal /CAS and the waveform determined by an access time (TAA) from an address signal are indicated on the same time axis. In the TCAC, data in the corresponding address has already been accessed at the trailing edge of the signal /CAS. On the other hand, in the TAA, since even after the signal /CAS has fallen, data in the corresponding address is accessed, data is defined at a lower speed as compared to the TCAC. Hence, the data definition is slower TAA than in TCAC by this access time, and previous data is continuously output during the access time in the HPM.
As shown in FIG. 1, a data output in the FPM cannot be maintained, when the signal /CAS becomes "H" level. On the other hand, in the HPM, even when the signal /CAS becomes "H" level, a data output is maintained, until memory data of the next address is accessed due to the next fall of the signal /CAS. As the operation frequency of a memory becomes higher and higher, a specification, which is difficult in the FPM, is available in the HPM.
FIG. 2 is a circuit diagram of a conventional output buffer which achieves data output in the HPM of a DRAM. Complementary signals RD and /RD input to an output buffer are data read from a memory cell. Complementary signals DXFR and /DXFR control clocked inverters 31 and 32, thereby controlling transference of the signals RD and /RD to the output buffer.
Data outputs from the clocked inverters 31 and 32 are respectively supplied to latch circuits 21 and 22. Each of the latch circuits is constituted by two inverters, the output of one inverter and the input of the other being connected to each other. An output of the latch circuit 21 is connected to the gate of a P-channel MOS transistor 11 via an inverter 25. An output of the latch circuit 22 is connected to the gate of an N-channel MOS transistor 12. The MOS transistors 11 and 12 are data outputting transistor circuits, and a common drain output of these transistors is connected to a data output I/O.
One of the inverters constituting the latch circuit 22 has a P-channel MOS transistor 41 for controlling a current path to a power source Vcc. An output of the inverter 25 is supplied to the gate of the transistor 41 through an inverter 42. The inverter 25 has an N-channel MOS transistor 43 for controlling a current path to a ground potential GND. An output from the latch circuit 22 is supplied to the gate of the transistor 43 through an inverter 44. These elements serve as a circuit for preventing a through current of the data output transistor circuits.
Gate control of the transistors 11 and 12 is achieved by supplying "HI" (high) or "L" (low) level signals to the gates of the transistors. Therefore, current consumption is efficiently reduced by a through current preventing operation in which a Vcc output from the inverter 25 first turns off the P-channel MOS transistor 11 and then turns on the transistor 42 and a Vcc output from the latch circuit 22 turns on the N-channel MOS transistor 12, or a through current preventing operation in which a GND output from the latch circuit 22 first turns off the N-channel MOS transistor 12 and then turns on the transistor 43 and a GND output from the inverter 25 turns on the P-channel MOS transistor 11. The above structure for preventing the through current is particularly significant in a multi-bit product.
FIG. 3 is a waveform diagram illustrating operations of the circuit shown in FIG. 2. Subsequently to the signal /RAS, an address signal in the memory is defined by the fall of the signal /CAS. Data in the memory corresponding to the address signal is transmitted as signals RD and /RD, which are determined after equalizing the "H" level in a data line. The signals DXFR and /DXFR are caused to be "H" level and "L" level respectively, so that new data of the signals RD and /RD are transferred to the output buffer shown in FIG. 2. The new data are output, while latch data previously output in the /CAS cycle is being reset.
The circuit configuration shown in FIG. 2 has the following drawback. In the latch circuits 21 and 22, new data cannot be output, until the output data in the previous cycle has been completely reset by the new data. Hence, the access time is increased, particularly when output data is full swing. In addition, since the through current preventing circuit is provided, the operations of the MOS transistors 11 and 12 at the final stage of the buffer are delayed due to feedback of a signal.
As described above, according to the conventional art, the output buffer having a function of consecutively outputting data in synchronism with a clock signal resets latch data in the previous cycle with newly transferred data. Therefore, it takes a considerable period of time to output desired new data, resulting in prevention of a high-speed access to a semiconductor memory.